1. Field of the Invention
The present invention relates to a semiconductor device, and in particular to a chip size package of a wafer level (WCSP), which packages a semiconductor chip in a wafer state.
This application is a counterpart of Japanese patent application, Serial Number 159341/2002, filed May 31, 2002, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, components for electric devices need small size and high performance with the advance of electric technologies.
Following such trends, chip size package (CSP) technologies have been introduced in the art of semiconductor packaging. These technologies can minimized the semiconductor package almost the size of the large-scale integrated circuit (LSI) chips.
To achieve the advance of productivity and the decrease cost, many companies and institutes are developing the practical CSP technologies, which are packaging a semiconductor chip in a wafer state (called a wafer level CSP as follows).
The technology of the wafer level CSP includes a step of forming conductive patterns and external electrodes on each semiconductor chip and a step of sealing each semiconductor chip by an insulated resin, which are performing in a wafer state without being separated into individual chips.
In addition, the conventional semiconductor device of wafer level CSP has a plurality of external electrodes arranging like an area array. Therefore, the conventional semiconductor device of wafer level CSP can be fit for the semiconductor chip needed many external electrodes to execute many commands.
However, the conventional semiconductor device of wafer level CSP, which is mounted on the printed board (the mother board), has a gap of the thermal expansion coefficient between the mother board and the semiconductor package. Especially, the gap is occurred between the mother board and the silicon chip including the wafer level CSP. As a result, during a thermal process, for example in the step of mounting the device on the mother board and the step of using the device, a large stress (a thermal stress) is occurred to the semiconductor device.
FIGS. 1(a) and 1(b) are sectional views showing a distribution of stress which is occurred by falling in temperature of the conventional semiconductor device of wafer level CSP, which has area type conductive pads, mounted onto the mother board. These figures are pattern diagrams showing simulated results. This simulation is performed under the condition that the temperature of the device changes from −40° C. to 125° C.
FIG. 1(a) is a plane view of the conventional semiconductor device showing the side of the device connected to the external electrodes. FIG. 1(b) is a cross sectional view of the conventional semiconductor device, viewed from 1-1′ line of FIG. 1(a). FIG. 1(b) shows an enlarged point of the conventional semiconductor device. In FIG. 1(b), the direction of the left side is nearing the center 508 of the package 500 and the direction of the right side is nearing the periphery 509 of the package 500.
As shown in FIGS. 1(a) and (b), during when the temperature of the device is falling, thermal stress occurs to the semiconductor device 500 due to contraction with the large difference in thermal expansion coefficients between the silicon chip and the mother board. The thermal stress occurring to the device 500 spreads from the right side to the left side in FIG.1(b), namely from the periphery 509 of the device 500 to the center 508 of the device 500.
The semiconductor package has a semiconductor substrate 502, conductive patterns 503 which are electrically connecting to a semiconductor element formed on the substrate 502, a sealing resin 504 which covers the substrate 502 and conductive patterns 503 and external electrodes 505. The semiconductor device comprises the mother board 501 and the package, wherein the package is mounted on the board via the external electrodes 505.
During when the temperature of the device is falling, the mounted semiconductor device has a large difference in thermal expansion coefficients between the silicon chip and the mother board (the thermal expansion coefficient of the silicon substrate is smaller than the thermal expansion coefficient of the mother board). Therefore, the thermal stress 506b, which is more than the thermal stress 506a of the semiconductor package (the semiconductor substrate), is applied to the mother board 501. There is a large gap of the thermal stress in the semiconductor device.
By this large gap, the great thermal stress is exerted on the external electrodes 505, e.g., solder balls, connecting to the mother board 501 and the semiconductor package. Especially, as shown in FIG. 1(b), thermal stress is concentrated to a point 507 of the external electrode 505 that is the end bonded to the semiconductor package and apart from the center of the device. The concentrated stress of the point 507 can damage the external electrode 505.
In the conventional semiconductor device, these stresses are exerted on the external electrodes and the conductive patterns, so that these stresses cause a problem, that is the damage of the external electrodes and the breaking of the conductive patterns, lead the low reliability of the semiconductor device.
JP-A-2002-280484 (Laid-open on Sep. 27, 2002) describes a chip size/scale package which has a resin post having roughness formed on the top of this resin post and covering a conductive layer. This resin post enables a stress to spread and absorb and strength of solder joint to be improved.
JP-A-2002-280487 (Laid-open on Sep. 27, 2002) also describes a chip size/scale package. This chip size/scale package has a metal post having a groove formed on the top of this metal post. This metal post enables a stress to spread and absorb and strength of solder joint to be improved.